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Xilinx is looking for a talented individual to join the Strategic Services team within Xilinx Wired and Wireless Group, in the position of a Sr. Staff Hardware Development Engineer. This person must possess a deep knowledge of, and strong experience in, modern FPGA design and verification methodologies (VHDL, Verilog, System Verilog, UVM) with a preference given to those with a background network and wireless security.
The successful candidate will work as a senior member of a team responsible for the development and functional verification of state-of-the-art FPGA-based Communications designs. Responsibilities include the specification, architecture, documentation, development, and verification of production ready wired and wireless FPGA based communications designs. The candidate must have excellent inter-personal and communication skills and be able to both work with and lead a multi-location team independently with little supervision.
Emphasis will be placed on having a background in wired and wireless communications security, protocols and algorithms as well as a proven track record specifying, developing, and verifying complex designs in FPGAs. It is expected that the individual will be detail oriented, thorough, and place great emphasis on quality processes and results.
Xilinx holds a leadership position in the FPGA and communications markets and is well positioned, from both a technical and business perspective, to drive the FPGA paradigm into advanced communications systems. This position offers candidates exposure to latest generation IP, tools, boards, and FPGA products, and the ability to use creativity and advanced design/test methodologies to develop state-of-the-art FPGA designs.
BS with 12+ years of exp or MS with 8+ years of exp or PhD with 5+ years of exp in Electrical Engineering or Computer Engineering or related equivalent
- Experience in ASIC or FPGA design/verification
- 10+ years of experience in industry standard EDA development and verification tools including the Xilinx ISE/Vivado tool sets.
- Expertise in VHDL, Verilog, System Verilog and UVM based methodologies
- Experience in documenting, implementing, and verifying complex design and verification platforms
- Experience in developing design and verification specifications and plans
- Excellent ability to analyze and isolate RTL and test bench issues
- Working knowledge of scripting languages such as Perl, PHP, TCL, and with C/C++ programming
- Excellent written and verbal communication skills.
- Positive attitude and good inter-personal skills
- HW behavioral modeling (System C, C/C++) is a plus
understanding of the following SW components:
- Ethernet drivers, Linux networking, TCP/IP
- SSL/TLS , IPSec (Open Source programming models) experience
- Client-Server architecture; API knowledge
- Software implementation experience in system level security data (packet) flows for L2/L3 and L4/L7 security protocols
- Knowledge of certificate authentication mechanism (X.509, CA etc.) for application/s processing
Hardware Security Experience:
- RTL implementation of security protocols: Ciphers, asymmetric crypto
- High speed packet processing and NIC function implementation
- DMA engines, memory interfaces (DDR, LPDDR, HBM) and packet buffers/ queues/ scheduling
- Search engines, packet classification, network statistics
- Knowledge of system level security data (packet) flows for L2/L3 and L4/L7 security protocols
- Address San Jose, CA, USA
- Salary Offer $50.000 ~ $100.000
- Experience Level Senior
- Total Years Experience 20+
- Academic Degree Bachelors